1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a multi-chip package which is capable of achieving light, thin and miniaturized packaging, while increasing capacity thereof.
2. Description of Related Art
Generally, in the construction of a plastic semiconductor package, a single semiconductor chip is molded by a resin such as epoxy molding compound, and forms a signal communication system using a lead frame having an outer lead to be mounted on a printed circuit board(PCB).
FIG. 1 is a sectional view showing a conventional semiconductor package.
Referring to FIG. 1, there are provided a semiconductor chip (or die) 1, a lead frame 2 which includes an inner lead 2a, an outer lead 2b, and a paddle 2c, and serves to support the semiconductor chip 1 and concurrently to form an electrical signal transmission path to the outside of chip. A metal wire 3 electrically connects the inner lead 2a of the lead frame 2 to the semiconductor chip 1, and a sealing body 4 seals the semiconductor chip 1, the inner lead 2a of the lead frame 2 and the metal wire 3.
As shown in FIG. 1, the semiconductor chip 1 is fixed to the paddle 2c of the lead frame 2 by means of an adhesive, and its pad electrode is electrically connected with the inner lead 2a of the lead frame 2 through the metal wire 3. A predetermined area including the semiconductor chip 1, the inner lead 2a of the lead frame 2, and the metal wire 3 is sealed by a plastic resin, to thereby form a rectangular type of package body, the sealing body 4. At both sides of the sealing body 4, a plurality of outer leads protruding from the sealing body 4 are separated from one another at predetermined intervals, to be mounted on the printed circuit board.
A manufacturing method of the plastic semiconductor package according to the conventional art includes the steps of: die-bonding the semiconductor chip 1 on the paddle 2c of lead frame 2; wire-bonding the semiconductor chip 1 on the paddle 2c to the inner lead 2a of the lead frame 2 by means of the metal wire 3; sealing the predetermined area including the semiconductor chip 1, the inner lead 2a of the lead frame 2, and the metal wire 3 to thereby form the sealing body 4; cutting dam bars (not shown) which functions to support each lead of the lead frame 2 by a trimming process; and folding the outer lead 2b protruding from the both sides of the sealing body 4 by a forming process. A semiconductor package fabricated through the above-mentioned processes, aligns the outer lead 2b thereof to printed metal line patterns of the board and is mounted by a re-flowing after a soldering, to thereby perform input/output operations of an electrical signal.
In the conventional semiconductor package, however, there is a problem in that the capacity of package is limited because the package body including the chip 1 is very thick, and has a large volume.
Further, there is a problem in that the conventional semiconductor package has a low reliability due to the physical properties of the wire as used in that bonding by the metal wire made of a materials such as an aluminum or gold can easily fail due to an exterior impact.
In addition, in case of a multi-level package where two or more semiconductor chips are installed in a single sealing body, the conventional semiconductor package has a limitation in achieving a light, thin and miniaturized package due to loop height of wire. Meanwhile, in the case where the two chips are facing to each other, there occurs a problem in that a manufacturing process becomes more complicated, the reason being that one chip must use a mirror chip that designes differently than the other chip. Moreover, the conventional semiconductor package suffers from a limited pin configuration due to the construction of the chip itself when the inner lead or multi-chip module for electrical conduction is designed.